TPMC630

Reconfigurable FPGA with 64 TTL I/O / 32 Diff. I/O TPMC630

Reconfigurable FPGA with 64 TTL I/O / 32 Diff. I/O

 

 

 

ПРОИЗВОДИТЕЛЬ: TEWS TECHNOLOGIES GmbH

ОПИСАНИЕ:

The TPMC630 is a standard single-width 32 bit PMC module providing a user configurable FPGA with 300,000 (TPMC630-1x) or 600,000 (TPMC630-2x) system gates. All local signals from the PCI controller are routed to the FPGA.

The TPMC630-x0x has 64 ESD-protected TTL lines, the TPMC630-x1x provides 32 differential I/O lines using EIA422 / EIA485 compatible, ESD-protected line transceivers. The TPMC630-x2x provides 32 TTL and 16 differential I/Os. All lines are individually programmable as input, output or tri-state. The receivers are always enabled, which allows determining the state of each I/O line at any time. This can be used as read back function for lines configured as outputs. Each TTL I/O line has a pull-up resistor. The pull-up voltage is selectable to be either +3.3V or +5V. The differential I/O lines are terminated by 120 ohm resistors.

The FPGA is configured by a serial Flash. The Flash device is in-system programmable via driver software over the PCI bus. An in-circuit debugging option is available via an optionally mountable JTAG header (on the backside of the board) for readback and real-time debugging of the FPGA design (using Xilinx ChipScope).

A programmable clock generator supplies up to six different clock frequencies between 200 kHz and 166 MHz. All outputs are available at the FPGA, one clock source is in addition used as the local clock signal for the PCI controller. The clock generator settings are stored in an EEPROM and can be changed by the driver software through PCI9030 GPIO pins.

The configuration EEPROM of the PCI controller can also be modified by the driver software, to adapt address spaces etc.

User applications can be developed using the design software ISE WebPACK which can be downloaded free of charge from www.xilinx.com.

The TPMC630 provides front panel I/O via a HD68 SCSI-3 type connector and rear panel I/O via P14.

Technical Specification:

 

Mechanical Interface

PCI Mezzanine Card (PMC) Interface, Single Size

 

Electrical Interface

PCI Rev. 2.1 compliant, 33 MHz / 32 bit PCI, 3.3V and 5V Signaling Voltage

 

PCI Target Chip

PCI9030 (PLX Technology)

 

Local Control Logic

TPMC630-1x: FPGA Spartan-IIE XC2S300E-6 FG456 I (Xilinx)
TPMC630-2x: FPGA Spartan-IIE XC2S600E-6 FG456 I (Xilinx)

 

TTL Line Transceivers

74LVT126

 

Number of Channels

TPMC630-x0x: 64 TTL I/O
TPMC630-x1x: 32 differential I/O
TPMC630-x2x: 32 TTL I/O and 16 differential I/O
TTL signaling voltage (maximum current: +/-24mA) or EIA-422/-455 signaling level

 

I/O Connectors

Front panel I/O HD68 SCSI-3 type connector (AMP787082-7)
PMC P14 I/O (64 pin Mezzanine Connector)

 

Power Requirements

(with Example Design)
TPMC630-x0x: 160mA typical (no load) @ +3.3V DC
TPMC630-x1x: 110mA typical (no load) @ +3.3V DC
TPMC630-x2x: 120mA typical (no load) @ +3.3V DC

10mA typical @ +5V DC (TPMC630-x0, when used as pull up voltage)
(+5V DC not used on TPMC630-x1x)
10mA typical @ +5V DC (TPMC630-x2x, when used as pull up voltage)

 

Temperature Range

Operating: -40°C to +85°C
Storage: -40°C to +85°C

 

MTBF

TPMC630-x0x: 407000 h
TPMC630-x1x: 451000 h
TPMC630-x2x: 428000 h

 

Humidity

5 - 95% non-condensing

 

Weight

80 g